VLSI Architecture of Reduced Rule Base Inference for Run-Time Configurable Fuzzy Logic Controllers

In this paper, a new VLSI architecture is provided for the application of quad-input and dual-output Fuzzy Logic Controller (FLC) with maximum seven fuzzy membership functions. Our approach is based on classical three stage implementation process – fuzzification, rule inference and defuzzification cores. An innovative design methodology is proposed by splitting the process between DSP processor and FPGA to implement run time configurable FLC. Since the target application takes a maximum of 4 inputs and 7 membership functions, the rule base comprises of 2401 (7) rules. It increases the complexity of the overall system. To minimize this effect, rule reduction VLSI architecture is suggested to bind the no of rules to 16 (2). The Rule inference is designed for seeking the maximum frequency of operation for targeted Virtex 5 LX110T FPGA. The simulation results obtained with Modelsim 6.3g show satisfactory results for all test vectors.